The present invention generally relates to the manufacture of semiconductor devices and, more specifically, relates to the manufacture of devices including multi-thickness silicide, multi-layered silicide and multi-thickness multi-layered silicide.
Integrated electrical circuit devices such as electrically erasable programmable read only memories (EEPROMs), transistors, diodes, thyristers and the like are usually manufactured on a semiconductor substrate, such as silicon. Such semiconductor substrates, even when doped, are usually more resistive than most metal-containing materials. Resistive contacts and interconnects are not desirable for electrical circuits due to the fact that resistance limits maximum current flow, may create heat, and may result in reduced circuit accuracy, consistency, and performance. Therefore, devices such as metal oxide semiconductor (MOS) transistors typically use a silicide or salicide layer over the source, drain and gate regions in order to reduce contact resistance. However, such transistors with silicide or salicide layers still tend to suffer from high contact resistance.
Transistors made on silicon-on-insulator (SOI) structures suffer from what is referred to as floating body effect (FBE) in addition to the above disadvantages. The FBE is when a body region voltage varies undesirably because the body region is electrically isolated from the substrate. The FBE introduces several undesirable characteristics. FBE causes, for example, sharp increases in the relationship between drain current and drain voltage (xe2x80x9ckink effectxe2x80x9d), anomalous subthreshold current, transient current overshoot, and early device voltage VDS breakdown. The kink effect may lead to lower device gain, which is undesirable in analog applications. The FBE remains a major obstacle to acceptable operation of SOI MOSFET transistors.
U.S. Pat. No. 5,352,631 addresses the above discussed disadvantages relating to contact resistance. In particular, U.S. Pat. No. 5,352,631 describes a method of forming one silicide species overlying the gate region, and another silicide species overlying the source and drain regions. However, there is no suggestion as to how to overcome the resistance associated with lightly doped drain and source regions (also referred to herein as source and drain extension regions). Further, there is no suggestion as to how to overcome the disadvantages due to the FBE.
In U.S. Pat. No. 5,965,917, one suggestion to overcome some of the disadvantages due to the FBE is to include a metal connector (electrical contact) that directly contacts a top silicide region, a side of a first doped region and a side of a body region. The disclosed device overcomes some of the disadvantages due to the FBE. For example, a voltage applied to the electrical contact sets the voltage of the body region because the electrical contact is directly coupled to the body region. However, there is no suggestion as to how to overcome the resistance in the lightly doped drain and source extension regions.
Therefore, there exists a need in the art for an electrical device which tailors resistance in the various regions such as the polysilicon regions of the source and drain regions, the junction regions of the source and drain regions, and the source and the drain extension regions. Further, there is a need in the art for an electrical device which, in addition to providing tailored resistance, also reduces the disadvantages due to the FBE associated with such devices on SOI structures.
According to one aspect of the invention, the invention is a transistor device formed on a semiconductor substrate having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and the drain include a main source and drain region as well as source and drain extension regions. Further, the device includes a multi-thickness silicide layer formed on the main source and drain a+ and the source and drain extension regions. Additionally, a portion of the a+ multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the multi-thickness silicide layer which is formed on the main source and drain regions.
According to another aspect of the invention, the multi-thickness silicide layer includes at least two layers of silicide of different species.
According to another aspect of the invention, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer interposed between the active layer and a main semiconductor substrate and wherein the BOX layer further defines the active regions.
According to another aspect of the invention, the semiconductor substrate is on a germanium-on-insulator (GOI) substrate.
According to another aspect of the invention, the invention is a method of fabricating a transistor device formed on a semiconductor substrate having active regions defined by isolation trenches. The method includes the step of forming a gate defining a channel interposed between a source and a drain formed within an active region of the semiconductor substrate. Further, the method includes forming a multi-thickness silicide layer on the main source and drain and the source and drain extension regions. Additionally, a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the multi-thickness silicide layer which is formed on the main source and drain regions.
According to another aspect of the method, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer interposed between the active layer and a main semiconductor substrate and wherein the active regions are further defined by the BOX layer.